For a digital signal in which a clock and data are combined, which is output from a transmitter, it is necessary for the clock and the data to be recovered at a receiver side. A clock data recovery (CDR) device for performing such recovery is described, for example, in Non-Patent Literature 1.
The clock data recovery device described in Non-Patent Literature 1 detects an edge of an input signal, recovers a clock based on a timing of the edge, and recovers data of the input signal at each timing indicated by the clock. A clock-generation device which generates a recovery clock in this clock data recovery device includes a phase lock loop (PLL) including a gated voltage controlled oscillator (GVCO), a frequency divider, a phase difference detector, an up-down counter, and a DA converter using a ΔΣ scheme.
The clock data recovery device described in Non-Patent Literature 1 is a device that operates in a burst mode. That is, the clock-generation device receives a reference clock from the outside before signal input start and during signal input, and outputs a clock at the same frequency as that of the reference clock. When the signal input is started, the clock-generation device matches a phase of the clock with a phase of the input signal in a short time, and outputs the clock.